SAN JOSE, Calif., 18 Feb 2015
March 2 - 5, 2015
Hilton Doubletree Hotel
San Jose, CA
At booth 505, Cadence is scheduled to showcase the latest tools, methodologies and support customers need for designing and verifying complex silicon, SoCs and systems. Experts will be on hand to discuss topics focused on Verification IP and IC/SoC/system design and verification.
Cadence is also scheduled to deliver several speaking sessions on system design and verification. The scheduled Cadence speaking slots are:
Monday, March 2:
- Tutorial 1: SystemVerilog Design: User Experience Defines Multi-Tool, Multi-Vendor Language Working Set
- Luncheon: What Is Needed to Drive Design Efficiency?
- Tutorial 3: Next-Generation Design and Verification Today
- Tutorial 4: SystemC Update and Tutorial
- Panel discussion: Art or Science?
- Lunch panel: Mastering Verification and Debug Productivity
- Panel: Is Software the Missing Piece in Verification?
- Tutorial 7: Verification 501: Graduate-Level Debug Tutorial
- Tutorial 10: Verification Solutions for ARM? v7/v8-Based Systems on Chips
Cadence also plans to deliver the following technical sessions at the conference:
Tuesday, March 3
- 9:00 am - 10:30 am PT - Session 2: Stimulus Generation
2.2: Automated Test Generation to Verify IP Modified for System-Level Power Management, Christophe Lamard of STMicroelectronics and Frederic Dupuis of Cadence
- 10:30 am - 12:00 pm PT - Session 4: Poster Session
4.13: Automatic Partitioning for Multi-Core HDL Simulation, Gaurav Kumar, Sandeep Pagey, Mohit Sinha, and Manu Chopra of Cadence
4.24: Conditional Delays for Negative-Limit Timing Checks in Event-Driven Simulation, Nadeem A. Kalil and David Roberts of Cadence
- 3:00 pm - 5:00 pm PT - Session 5: Testbench Construction
5.1: Methodology to Port a Complex Multi-Language Design and Testbench to Simulation Acceleration, Horace Chan and Brian Vandegriend of PMC-Sierra, Inc., and Efrat Shneydor of Cadence
5.3: An Easy VE/DUV Integration Approach, Uwe Simm of Cadence
- 3:00 pm - 5:00 pm PT - Session 6: Advanced Techniques
6.3: Automated Performance Verification to Maximize Your ARM v8 Pulling Power, Nicholas A. Heaton of Cadence and Simon Rance of Atrenta Inc.
- 3:00 pm - 5:00 pm PT - Session 7: Multi-Language
7.3: Parameter Passing from SystemVerilog to SystemC for Highly Configurable Mixed-Language Designs, Bishnupriya Bhattacharya, Samik Das, Zhiting Duan, Chandra Sekhar Katuri, and Pradipta Laha of Cadence
- 10:00 am - 12:00 pm PT - Session 10: User Perspectives
10.3: Whatever Happened to AOP? James P. Strober of Ciena, Corp. and Corey Goss of Cadence
- 3:00 pm - 4:30 pm PT - Session 13: Coverage
13.2: Coverage-Driven Generation of Constrained Random Stimuli, Marat Teplitsky, Amit Metodi, and Raz Azaria of Cadence
13.4: Navigating the Functional Coverage Black Hole: Be More Effective at Functional Coverage Modeling, Jason Sprott of Verilab, Inc. and Matt Graham of Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, automotive electronics, and computer systems. The company is headquartered in San José, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.basilicius.com.
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