- Digital verification best practices extended for mixed-signal IP and SoCs
- Methodology rigor to more quickly achieve verification closure
- Advanced power management feature coverage
In today’s SoC designs, the level of interaction between analog structures and digital logic is dramatically more complex than in the past, where divide-and-conquer approaches to design and verification proved adequate. This interdependency creates a requirement for a mixed-signal approach to verification.
Mixed-signal verification, at its root, still begins with analog behavior being captured and simulated within the analog design environment. However, as the analog and digital blocks are merged, using even the fastest analog circuit solvers becomes a runtime bottleneck in the verification closure process.
At the SoC level, therefore, you need a way to quickly model your design with enough accuracy for your application. Using real number models (RNMs) and an assertion-based approach, Cadence’s mixed-signal verification flow and methodology brings together the analog and digital sides. Integrating analog behavior modeling and analog and digital solvers into one flow, the methodology lets you balance the right amount of accuracy and speed based on your design requirements. The flow delivers:
- Flexibility to trade off between speed and accuracy based on your design’s requirements
- A single verification environment combining both analog and digital solvers that can be used to functionally verify at the desired level of accuracy using either option or both digital (speed) and analog (accuracy) engines
- Metric-driven verification (MDV) to analog components in a mixed-signal design
- Complex checkers that can check for any combination of cross-domain analog and digital sequences
- Throughput to support large regressions
- Power-aware mixed-signal verification
Bringing Assertion, MDV, and Plan-Driven Verification to Mixed-Signal Designs
Digital designs have long had the benefit of MDV, where verification plans are tailored to given specifications, progress is tracked closely, and designers can determine exact verification coverage levels. Analog designers continue to focus on designing and verifying high-performance analog, zeroing in on analog parameters including transient and DC analysis. At the SoC level, they integrate the analog as black boxes. The SoC verification engineer typically ignores analog functionality and performs bare-minimum testing, with very limited interaction between digital and analog blocks. This approach results in errors and re-spins.
Cadence has solved the problem by pioneering the application of advanced digital verification methodologies to include analog. Our digital/mixed-signal flow allows the application of MDV to the full SoC by enabling randomization, as well as functional coverage on analog along with the use of real number modeling (RNM). Advanced testbench creation methodologies like the Universal Verification Methodology (UVM) are also supported together with verification planning and complex mixed-signal assertions that go between the domains. (Check out Cadence's Mixed-Signal Methodology Guide at your favorite bookseller.)
To support these advanced verification techniques, the analog side of the house has several advanced capabilities. The Virtuoso? schematic model generator (SMG) enables the creation of wreal models of analog. The amsDmv tools enable validation of these behavioral models for functional equivalence against the analog design, comparing the representation of the same design at different levels of abstraction. Virtuoso Verifier allows collection of analog coverage of the analog design within the Virtuoso custom and analog design environment.
In addition to tapping into our Virtuoso environment, our digital/mixed-signal verification flow also takes advantage of our Xcelium? Parallel Logic Simulation. As you move your design to a higher level of abstraction, the flow provides an increased level of automation and real-time modulation. Eventually, all aspects of the design could be driven by MDV methodology, with prepackaged UVM components. To enable power-aware verification, Xcelium simulation also supports CPF and UPF-IEEE 1801 standards for both digital and mixed-signal designs. With Cadence’s complete digital/mixed-signal verification flow, you’ll be able to address all aspects of the verification process, while balancing the needs of speed versus accuracy in a unified environment.
Because today’s mixed-signal designs have multiple feedback loops through analog and digital domains, the “black box” approach is no longer possible for top-level verification. The new world is a complex, multilayered fusion of the two disciplines, where the boundaries are fuzzy and the interactions complex and, at best, poorly modeled. Cadence offers an integrated mixed-signal verification environment that ensures the reliability of the mixed-signal verification results.