The Cadence??Conformal??Litmus Constraints and CDC Signoff is the next-generation solution that provides the fastest path to SoC-level constraint signoff and CDC signoff. It is the industry’s first constraint signoff solution with an integrated static timer (from the Tempus? Timing Signoff Solution) and provides customers with 100% accuracy at the register-transfer level (RTL).
The Cadence??Conformal??Constraint Designer provides a complete and efficient path to develop and manage constraints and clock-domain crossings (CDCs), ensuring they are correct from RTL to layout. By pinpointing real design issues quickly and accurately, delivering higher quality timing constraints, and finding issues with clock-domain synchronizers, the solution helps you reduce overall design cycle times and enhance the quality of silicon in complex SoC designs.