Silicon signoff and verification encapsulates a set of tools that address a series of electrical and physical signoff and verification steps that designers must perform on their design before tapeout. These steps report errors that require iterative and incremental fixes, also called engineering change orders (ECOs), ensuring the design integrity from an electrical and physical standpoint.
There are three main challenges designers face while designing complex SoCs:
- Performance and Capacity – Signoff tools take too much time and use too much memory
- Accuracy – As we move to deeper submicron nodes, it’s more of a challenge to match early synthesis and implementation estimates of timing, placement, power, and extraction during signoff
- Design Closure – Traditionally, signoff tools have been only able to report on design issues, but have not been able to actually fix them once they are detected. This has resulted in a lot of back and forth between implementation and signoff, greatly increasing time to market
At Cadence, we recognize the need for this last step to converge faster, and for you to be able to tape out with far fewer iterations than has been historically possible. At the same time, we also recognize the need for these runs to be fast enough. To this end, we have designed a solution that has the following benefits:
Massively Parallel, Cloud-Ready Solutions
Our signoff tools, the Quantus? Extraction Solution, Tempus? Timing Signoff Solution, Voltus IC Power Integrity Solution, and Pegasus? Verification System, are all cloud ready and have been built to run on massively parallel server farms. These server farms can reside internally within the company or externally at a cloud provider. Your design is automatically partitioned into smaller instances, is split up across multiple machines and CPUs, exploits multi-threading, then balances the load between machines and CPUs through adaptive scheduling. Several of our customers have been using these new tools and have seen performance speedup in the orders of magnitude.
Integrated Engines for Accuracy and Faster Design Convergence
The Cadence? digital design flow now uses integrated engines for timing, placement, power, and extraction throughout its flow from the Genus? Synthesis Solution all the way to silicon signoff with the Tempus and Quantus solutions, Pegasus system, Design for Manufacturability (DFM) solutions, and Voltus? power solution. Referred to as “in-design verification”, this flow leverages signoff verification solutions to avoid any correlation and consistency issues that will penalize the designer during the final stage before tapeout. For instance, this means that when the Genus solution runs synthesis earlier in the design cycle, it uses the same placement and routing that the Innovus? Implementation System would during the implementation, and can make better choices earlier in the design cycle where issues are easier to fix. And, in the Innovus system, designers can run the Tempus Timing and Voltus Power solutions, as examples, to close timing faster at tapeout. This causes far fewer iterations later in the design and much faster convergence during signoff. This in-design capability with integrated engines also eliminates, or greatly reduces, the need for designers to build in significant pessimism into their design budgets, greatly improving power, performance, and area (PPA) in the process.
Tools that Fix Problems When They Find Them
The integrated engines in our signoff tools have been designed to not only analyze problems early on in the design flow, but to also fix them as needed, resulting in far fewer back-and-forth iterations between implementation and signoff. Our tools can find the problems, analyze various scenarios, choose the best PPA optimization available, and implement them early in the design flow, resulting in designs that come within 2% to 5% of signoff metrics for PPA closer to tapeout.
Mixed-Signal and Custom Design Support
All of Cadence’s signoff tools or capabilities are integrated in the Virtuoso? platform, providing the same capabilities for mixed-signal and custom designs.
Silicon signoff and verification is the crucial last step that gates signoff in every design flow. Using the Cadence design flow with our integrated engines and massively parallel tools will enable this process to be far smoother and will ensure faster design closure with much improved PPA.
Our 7LPP process provides the best power, performance and area that we have seen so far in advanced FinFET nodes, and we expect this will provide great benefits for our mutual customers’ next generation SoC designs.
Ryan Sanghyun Lee, vice president of the Foundry Marketing, Samsung Electronics
We’ve verified that the Cadence methodology meets our accuracy, frequency, power and cell utilization requirements. The certification of the Cadence digital tool suite allows our mutual customers to reach their PPA targets and to experience the benefits associated with the GF 22FDX body bias techniques ...
Richard Trihy, senior director, design enablement, GLOBALFOUNDRIES
4. The Voltus IC Power Integrity Solution provided several efficiencies that enabled us to shorten the time to design closure on our largest ever switch-chip FinFET design so that we can stay in front of the competition. Given our successful, accurate silicon results, we’re planning to use Voltus ...
Sanjay Kumar, senior director ASIC Designs, Juniper Networks