Cadence is committed to keeping design teams highly productive. A range of support offerings and processes helps Cadence users focus on reducing time-to-market and achieving silicon success. Overview
- Rapid evaluation and feasibility of potential interconnect pathways in a single-canvas view of die/package/PCB substrates and cross-substrate interconnect
- Efficient evaluation and tradeoff providing better prediction of cost and performance using well-qualified design definitions
- A smooth predictable path to optimized in-substrate and cross-substrate routing
- Optimized signal performance while minimizing overall design time by avoiding late-cycle design changes
Almost every chip must be packaged and then designed into a system or subsystem that is usually represented as a PCB. Signals, especially important signals that must perform to a protocol standard such as DDRx memory or high-speed serial such as PCI Express? (PCIe?) Gen2/3, must transition across the three or more very different substrates and reach their target within specification.
Against them are the materials and properties of the substrates, and of course the interconnect pathways between the substrates and their transition points (die bumps, package BGA balls, and PCB breakout pattern). This system-level interconnect is summarized in Figure 1.
In every semiconductor company or systems company that is designing an IC is a person or persons responsible for defining the IC bump and package ball arrays or patterns and signal, power, and ground assignments. It’s very common for this to be done using spreadsheets, such as the one in Figure 2.
The problem with spreadsheets is that they are manual, error prone, use static data from the design tools, and cannot effectively or efficiently communicate interconnect routing instruction or constraints to the upstream and downstream implementation tools. Yes, spreadsheets can be effective for pin and net assignments, but what about:
- Signal/power/ground (SPG) ratios and patterning to ensure quality return paths and power delivery
- Route pathways for escape sequencing, layer assignments, and feasibility
- Bottom-up or PCB-driven assignment, or pin compatibility with previous-generation designs
- Diff pair management and propagation across the substrates
Using spreadsheets can now be a thing of the past as multi-substrate interconnect exploration, definition, and design can now be done in Cadence’s integrated solution (Figure 3): Cadence? OrbitIO? Interconnect Designer and Cadence SiP Layout.
The OrbitIO Interconnect Designer transforms the cross-substrate interconnect architecting, assessment, implementation, and optimization process by unifying IC, package, and PCB data in a single environment where signal-to-bump/ball-assignment and connectivity/routing-pathway scenarios are easily derived and evaluated in the context of the complete system prior to implementation. Full system visualization and a unified data model enable rapid exploration and propagation of changes to adjacent substrates, providing instantaneous feedback on their system-wide impact. OrbitIO Interconnect Designer helps the engineer/architect achieve the right balance of cross-substrate interconnect integration for optimal performance, cost, and manufacturability prior to implementation—resulting in fewer iterations and shorter cycle times.
Within a single graphical, lightweight, and easy-to-use environment (Figure 4), the following can be rapidly explored, defined, and communicated:
- Geometrical definition of bump and ball pad patterns
- Pin-based floorplannin
- Allocations of pins or regions for use by specific signal types or interfaces
- Power delivery and return path planning
- Netlist definition and management
- Propagation and mapping of nets between fabrics
- Route pathway exploration, definition, and optimization
- Connection sequencing and assignment
- Evaluate route feasibility
- Communication of results and intent to the fabric implementation teams
OrbitIO Interconnect Designer does not restrict you to a single methodology, instead it has been designed to enable the most common interconnect pathway methodologies commonly used today:
- IC/PC-driven package BGA ball map design and optimization, including PCB schematic symbol generation (DE-HDL support)
- IC-driven BGA ball map design and optimization
- Cross-substrate IC bump array and package ball definition and optimization with route pathway design including PCB
- Early package start-from-nothing BGA ball map creation
- Package BGA-driven IC bump array design and optimization
- Package BGA ball map-based design and optimization targeting multiple PCBs (variants-based design)
Figure 5 shows an example of the first methodology. Here a pre-placed PCB with two fixed DDR3 memory devices is driving the assignment and route pathway plans onto the package BGA and up to the IC bump array.
Once the critical signals and buses have been explored, defined, and evaluated, the resultant pathways can be handed off to the respective substrate implementation designers and design tools for detailed manufacturing rules-driven implementation (Figure 6).
With OrbitIO Interconnect Designer and SiP Layout solution, you now have an environment for the rapid evaluation and feasibility of potential interconnect pathways in a single-canvas view of die/package/PCB substrates and cross-substrate interconnect. This solution enables efficient evaluation and tradeoff providing better prediction of cost and performance using well-qualified design definitions. Direct integration with the IC implementation tools (Innovus? and Virtuoso? solutions) as well as the IC package implementation tool (SiP Layout) provides a smooth predictable path to optimized in-substrate and cross-substrate routing, leading to optimized signal performance while minimizing overall design time by avoiding late-cycle design changes.
Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview