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- Shorter cycle times and predictability with multi-fabric planning
- Supports bottom-up PCB influenced planning of silicon and package
- Design data compatibility with OSAT providers
The Cadence? OrbitIO? interconnect designer revolutionizes the cross-fabric planning and assessment process by unifying silicon, package, and board data in a single canvas environment, enabling engineers to achieve the optimal balance of connectivity for performance, cost, and manufacturability prior to implementation—resulting in fewer iterations and shorter development cycles.
Conventional design methodology has been a serial top-down approach where the silicon drives downstream connectivity with minimal upstream feedback, with data communicated using static spreadsheets. Growing functional integration at both the die and package level, combined with the latest high-performance interfaces, requires greater planning and coordination across all fabrics to achieve product performance objectives, leaving little room for inefficient and error-prone methodologies.
The OrbitIO system planner provides an environment capable of uniting design content from various sources for the purpose of planning, then communicating the data back to their respective implementation tools for completion. It enables rapid exploration and evaluation of connectivity scenarios providing immediate feedback on the impact to adjacent devices and fabrics. Planning results and route plans are directly exchanged with package design resources whether it’s an internal group or outsourced assembly and test (OSAT) provider.
As part of an overall Cadence co-design solution, OrbitIO interconnect designer can seamlessly exchange silicon, package, and PCB data with their corresponding implementation tools.
Silicon considerations can guide downstream connectivity in a top-down flow, or PCB level considerations can drive upstream connectivity in a bottom-up flow. The OrbitIO interconnect designer’s flexible and adaptable environment also supports a middle-out flow where package-level considerations can simultaneously drive die and PCB connectivity.
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