Length : 3 days
This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.
This course gives you an in-depth introduction to the main SystemVerilog enhancements to the Verilog hardware description language (HDL) for verification only. The course discusses the benefits of the new features and demonstrates how verification and testbench design can be more efficient and effective when using SystemVerilog constructs.
You?first examine the basic SystemVerilog enhancements useful in verification, such as new data types, subprogram enhancements, packages, and interfaces. The course then explores verification features such as classes, constrained random stimulus, and coverage.
This three-day class is an abridged version of the five-day SystemVerilog Language and Application course, with the?emphasis on the verification features of SystemVerilog. It is aimed at the verification engineer who will not use SystemVerilog for RTL design.
After completing this course, you will be able to:
- Understand and use basic SystemVerilog features, including new data types, literals, statements, and operators; enhancements to tasks and functions; and packages and interfaces
- Appreciate and apply?SystemVerilog verification features, including classes, constrained random stimulus, coverage, strings, queues and dynamic arrays, and learn how to utilize these features for more effective and efficient verification
Software Used in This Course
- Xcelium? Single Core
Modules in this Course
- SystemVerilog Overview
- Standard Data Types and Literals
- Procedures and Procedural Statements
- User-Defined Data Types and Structures
- Hierarchy and Connectivity
- Tasks and Functions
- Simple Verification Features
- Random Stimulus
- Basic Classes
- Polymorphism and Virtuality
- Class-Based Random Stimulus?
- Interfaces in Verification
- Covergroup coverage
- Queues, Dynamic?and Associative Arrays (QDA)
- Verification engineers
You must have:
- The ability to navigate a file system and use a text editor
- A basic understanding of digital hardware design and verification
- Experience with or knowledge of the Verilog hardware description language