Length : 1 day
This is an Engineer Explorer course for designers familiar with synthesis using the Genus? Synthesis Solution.
In this course, you explore and implement several low-power techniques to reduce both dynamic and leakage power during synthesis. You use multiple supply voltage (MSV) design, power shutoff (PSO) synthesis and dynamic voltage frequency scaling (DVFS) synthesis. You run low-power flow using CPF and IEEE 1801 and troubleshoot a low-power design. You apply formal verification to validate your power constraints and ensure the functionality of a low-power design.
Here is the sample video from the course.
Note: This course is based on the legacy user interface and not the common user interface.
After completing this course, you will be able to:
- Identify power reduction techniques
- Set up and run low-power synthesis flow
- Enable clock gating
- Annotate switching activity and run RTL power estimation
- Run optimizations to reduce dynamic and leakage power consumption
- Implement a power shutoff (PSO), dynamic frequency voltage scaling (DVFS), and multiple supply voltage (MSV) design using CPF
- Use IEEE 1801 for designs with MSV and PSO methodology
- Analyze power results
- Troubleshoot low-power design
- Analyze a low-power design with Conformal? software
Software Used in This Course
- Conformal Low Power XL
Genus 16.2 ISR1, CONFRML 16.2
Modules in this Course
- Introduction to Low-Power Implementation Solutions
- Power Reduction
- Low-Power Synthesis Flow
- Low-Power Methodologies: MSV, PSO and DVFS
- Troubleshooting Low-Power Design
- Checking Low-Power Designs with Conformal Software
- ASIC Designers
- Chip Designers
- Digital IC Designers